1. Technical Field
Aspects of the present disclosure relate in general to computer architecture and electronic circuitry. In particular, aspects of the disclosure include a high-speed communication bus interface with an adaptive swing driver to reduce power consumption.
2. Description of the Related Art
As microprocessors computer memory, communications interfaces and other devices increase in speed, the connections between these discrete devices, via a high-speed communication bus also must increase in speed and throughput. As with most components, for high speed parallel bus transmission, power consumption and transition time are the major concerns. With wide parallel bus transmission, the power summation of each signal unit is large and the transmission speed limited by transition time. A faster transition time results in higher transmission speeds.
As integrated circuit (IC) density increases, such as with 2.5-dimensional (2.5 D) or 3-dimensional (3D) integrated circuit processes, the amount of pins in a parallel data bus increases from tens to thousands of pins. The greater the data bus transitions, the more power the data bus consumes.
In current designs, parallel data busses use a termination scheme to limit signal swing for high speed transitions. However this termination scheme consumes high direct current (DC) power. With the advent of 2.5 D or 3D integrated circuit parallel busses, the power consumption is even higher.
In yet another current parallel data bus design, the parallel data bus uses full swing signals with a normal level power supply to get slight DC power consumption. As expected, this results in large signal swings with great transition times, thus limiting the transmission speed.